SiGe 43.2 Gb/s 4:1 Multiplexor and Clock Multiplier for OC-768 Fiber Communications

Abstract

We have developed a Clock Multiplying Unit and 4 to 1 Multiplexor (CMU / MUX 4:1) that operates up to 47Gb / s. The on board VCO is LC tuned and the output clock jitter is 4pspp. The eye diagram of the output is 400mV swing with rise and fall times of less than 9ps. This integrated circuit was processed in a 120GHz BICMOS 0.25um process. Power dissipation is only 1W for a chip area of 2mm^2.

Introduction

The next generation of optical fiber communications will require transmission speeds of higher than 40Gb/ s. The OC-768 Synchronous Optical Network (SONET) standard with Forward Error Correction (FEC) will run at 43.2 Gb / s. Silicon Germanium (SiGe) Technology, with unity current gain frequency (Ft) of higher than 120GHz is perfect for this market, being integrated with CMOS on 8 inch wafers, at very high yields.

This publication describes a 4 to 1 multiplexor (mux) with integrated clock multiplying unit (CMU) phase locked loop (PLL), which achieves 43.2 Gb / s operation with good 0.4V 'eye' opening and low 4pspp jitter. Four inputs at 10.8Gb / s (SONET OC-192 with FEC) are time multiplexed to the higher 43.2 Gb / s rate. A 2.7GHz or 675MHz reference is multiplied by the PLL to the half-frequency of 21.6GHz. The output is clocked and multiplexed by both levels of our very symmetric clock, to eliminate duty cycle related jitter. The CMU requires a single external capacitor, or RC network, for filtering. This integrated circuit was also produced without the PLL, for laboratory test use, where a high quality 21.6GHz synthesizer with very low jitter is available. The stand-alone 4:1 Mux jitter is less than 3pspp, limited by measurement accuracy. A companion 1:4 demultiplexor (demux) that also requires external clock was also developed for bit-error-rate (BER) testing of the multiplexor.

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