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Semiconductor Packaging, Fatigue Failure Expert Consultant Resume

Resume of RIJ Consultant
Principal Industries Served:
  • Medical Devices and Equipment
  • Semiconductor Packaging

Education:

This expert received both an M.S. and a B.S. in Mechanical Engineering from Southern Methodist University.


Expertise and Services:

Semiconductor Packaging, Fatigue Failure Expert Consultant Resume

This expert specializes in product design and development, project management, R&D, and process reengineering in industries with technical specialties. Further specialties include non-linear and dynamic analysis as well as fatigue and fracture mechanics.

Expertise includes CAD complements FEA usage, product design studies and optimization, product and process reliability, and manufacturing. Additional expertise includes inspection, shipping, and composite coating process of pyrolytic carbon component and tissue manufacture.

Additional experience and specialization includes electronics packaging, PCB component layout design, PCB drop-test reliability, and structural and digital electrical design. Further experience includes FEA modeling, solder fatigue life, structural analysis, and spice decks. More experience includes frequency domain analysis, inductance modeling, and impedance analysis. Has conducted numerous studies in areas including rapid attach heart valve design, and semiconductor packaging.


Professional Experience:

Consultant, Kevin Kennedy Associates Inc.

Providing mechanical engineering, management consulting, process engineering, semiconductor packaging engineering, engineering, consulting, failure analysis, forensic engineering, and related expertise to a wide variety of clients.

Manager, Process Engineering, Major Medical Equipment Manufacturer

Was responsible for the exact reliability of products and process (manufacturing, inspection, and shipping). Designed new products which required intimate knowledge of material limitations and manufacturing capabilities. Diverse materials knowledge with the composite coating process of making pyrolytic carbon components and tissue manufacturing.

Semiconductor Packaging Engineer, Texas Instruments, Dallas, TX

Led a multi-million dollar international R&D electronics packaging project. Structural analyst for PCB component layout design for drop test reliability at TI. This included developing PCB drop-test design rules guideline document for TI's cell phone customers. Provided structural and digital electrical design and analysis to internal and external customers. Key development areas include developing more predictive FEA modeling in static and dynamic non-linear thermo-mechanical warpage and solder fatigue life and structural analysis for 300mm CMOS manufacturing process development. Experienced electrical analyst with creating and using spice decks, frequency domain analysis, inductance modeling, impedance analysis, and design optimization.

Application Engineer, Parametric Technology Corp. Dallas, TX


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Pete specializes in microelectronics manufacturing, intellectual property analysis and valuation, semiconductor equipment and patent infringement.

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