Principal Staff Engineer, DRAM Technology Dept., Semiconductor Products Sector, MOS Memory Products Division, Motorola, Austin, TX
Responsible for the Device Engineering activities to support the transfer of Toshiba 1M and 4M DRAM technology into production in Motorola and joint venture wafer fabs. Analyzed wafers, product and data from all fabs and compared the performance of the fabs to ensure that the process was matched and that the product was consistent from all wafer fabs, including modeling, parametric test, failure-analysis, and process characterization. Also supported other Motorola product and development groups with modeling, and device test and characterization. Provided engineering support for fab startup and production problems at all facilities including qual fail issues, yield issues and process improvements.
Principal Device Engineer, Bipolar Technology Development, Advanced Micro Devices, San Antonio, TX
Process and Device modeling and simulation in support of the development of advanced Bipolar processes. Developed models for dual-poly-emitter Bipolar devices from process definition through SPICE model decks, resulting in circuit performance modeling to within 10% of the initial Silicon, and continued this function through the technology exchange joint venture with Sony Corporation who subsequently bought the venture.
Process Development Engineering Manager, Fab X, Advanced Micro Devices, Austin, TX
Head of the engineering department responsible for the Device Engineering, Process Integration and yield enhancement functions. Developed new process technologies including the 64K DRAM, nMOS SRAM and a triple-poly (1.0 um) 16K FSRAM.
My group created and brought into production the process to produce the second-source Intel 80186 and 80286 processor families with superior performance, costs and yields versus the Intel process. Accountable for wafer sort, laser, parametric test, and yields in a then state-of-the-art 5" MOS wafer fab.
Device Engineering Supervisor, Modeling Department, Mostek Process R&D, Carrollton, TX
Lead the group that was responsible for the characterization of process experiments in support of the development of 64K, 256K and 1Mbit DRAM process technologies.
I was one of the principal contributors to the development of the process test vehicles and directed the layout of those designs. Designed the process verification structures, the test structures for the verification of design rule limitations, and defect arrays. One of the primary authors of the Design Rule Manual and the principal author of the Layout Design Rules and the modeling decks. Directed efforts toward HCE testing and transistor and interconnect reliability screening for process R&D. Supported Process R&D with modeling using SUPREM, SEDAN, Minimos and other tools. Developed the circuit models for the 64K cell/bitline structures and improved Mostek's proprietary SPICE model equations.
Bipolar Product Engineering Manager, Semiconductor Division, Data General Corp., Sunnyvale, CA
Responsible for process integration, device engineering, parametric testing, and new product introduction for bipolar product lines of >150 products. Process technologies ranged from diode arrays to bit-slice microprocessors and PALs. We produced every chip in the Nova and Eclipse computers. Author of the Composite Schottky Design Rules used for PALs, PROMs and uP's as well as the ECL design rules for gate array projects. Designed the process development test vehicles and supported the process development efforts for all processes.
Product Engineer, Monolithic Memories, Inc., Sunnyvale, CA
Responsible for the 8M family of Bipolar PROM's, PAL's, and the introduction of a new line of interface chips. Also helped debug and fix several process problems in support of the startup of a new 4” wafer fab.
Semiconductor device and product engineer, expertise on device or transistor design, product and process development, yield enhancement and process improvement. Assist product development projects (chip industry), with model validation, silicon verification and foundry selection and management. Manage failure analysis, reliability testing, and final test and assembly programs. Ensure success of first-rev silicon, provide support for redesign success. Provide project planning and management, and full business plan development consulting for startup or critical projects. Consultant to wafer fabricators for yield enhancement, problem solving, and process and operational improvement. Expert witness testimony, and patent infringement litigation, including analyses, opinions and testimony. Investment advisors for semiconductor products, processes, and wafer fab and equipment issues, technologies, needs and trends.
Multi-national technology exchanges with Japanese, Korean, UK, and Israeli operations, with consulting experience with operations in the US, Mexico, Japan, China, Taiwan, Singapore, France, and Italy
Participated in nine wafer fab startups at every level from NCG to Director of Engineering
Product lines include DRAM, SRAM and NVM, Microprocessor, Mixed-signal, Analog, Discrete RF and Power
