System-On-Chip (SOC) Testing, Integrated Circuit Expert Consultant Resume

• Computer Science
• Electrical and Computer Engineering
• Research

This expert has a Ph.D. and an M.S.E. in Computer Science and Engineering, both earned through the University of Michigan in Ann Arbor, MI.

This expert has a B.Tech in Computer Science and Engineering, earned through the Indian Institute of Technology in Kharagpur, India.

System-On-Chip (SOC) Testing, Integrated Circuit Expert Consultant Resume

This expert specializes in integrated circuit testing, design for testability, and microfluidic biochips. This expert has knowledge in real-time embedded systems and wireless sensor networks.

Areas of research interest this expert is involved with include computer-aided design and testing of VLSI systems, design automation and testing of microfluidics-based biochips, and cooling and thermal management of integrated circuits using droplet-based microfluidics. This expert has knowledge in wireless sensor networks, ad hoc vehicular networks, delay-tolerant networking, and real-time embedded systems.

This consultant pioneered research on the testing and design for-testability of core-based system-on-chip (SOC) integrated circuits, and has been a leading influence worldwide in the emergence of this research area. This consultant was the first to define the problem of SOC test planning, developing the earliest optimization techniques and mathematical models for SOC test automation. This consultant is the author/co-author of the first published papers on SOC test scheduling, wrapper design and optimization, and test access mechanism optimization. With a collaborator at Philips Research Labs, this consultant developed a set of benchmark SOCs that have been widely used in the research community. This consultant has led the field with innovations in test planning for hierarchical SOCs, testing of mixed-signal SOCs, the use of virtual test access mechanisms, thermal-aware test scheduling, wafer-level testing of core-based SOCs, and interconnect/signal integrity testing for core-based SOCs.

Other noteworthy areas of expertise this consultant has include test data compression for integrated circuits, with work based on compression codes, such as the Golomb code, the FDR code, the alternating run-length codes, dictionary-based compression, built-in self-test, and test response compaction.

This consultant is an expert in design automation for microfluidics-based biochips, being the first to relate microfluidic biochips to electronic design automation. This consultant is recognized as a pioneer in this area with publications and tutorial papers on synthesis, simulation, and testing. This consultant is a frequent IEEE Distinguished Speaker on system design issues related to biochips, and has delivered numerous keynote and invited talks at conferences.

As an expert in embedded real-time systems, this consultant developed the first unified framework for dynamic power management and run-time fault tolerance. This expert pioneered research on device scheduling for dynamic power management in hard real-time systems. This expert has authored influential paper on network flow techniques for dynamic voltage scaling in hard real-time systems.

Specializing in wireless sensor networks, this consultant made fundamental contributions to algorithms for sensor node deployment, coverage enhancement, and network self-organization.

With collaborators, this consultant developed the theory of identifying codes on graphs, which has been studied extensively since then in the Information Theory community.

Graduate Research Assistant, Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI

Consulting Positions

Consultant, Johnstech International Corporation, Minneapolis, MN

Consultant, Spectrum Sciences & Software, Fort Walton Beach, FL

Technology Evaluation Consultant, Advanced Technology Ventures, Waltham, MA