Home Electrical Engineering A SiGe 10-Gb/s Multi-Pattern Bit Error Rate Tester

A SiGe 10-Gb/s Multi-Pattern Bit Error Rate Tester

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In this paper we present a monolithic IC that is capable of generating and evaluating multiple pseudo random bit sequences (PRBS) from DC to 10-Gb/s. This IC could be used as a low cost substitute for more expensive bit error rate test (BERT) systems.


Due to recent advances in high-speed communication systems, reliable testing of these systems has been an issue of concern. Pseudo random bit (PRB) sequences provide a convenient way of testing these high-speed components, and are mainly used for bit error rate and jitter measurements. The response of the device under test (DUT) for different pattern lengths often gives useful hints about the performance of the DUT. For example, a clock data recovery (CDR) unit will show higher jitter at longer pattern lengths due to the high run-length of ones and zeros in the pattern. A standard PRB sequence has a mark density ratio (defined as the average ratio of number of zeros to ones in a sequence) of 1/2. Modified PRB sequences that have mark densities other than 1/2 are used to characterize the dc behavior of the DUT. There have been monolithic bit error rate tester (BERT) IC's developed in the past, which have one or two patterns. None of them have patterns longer than 223 -1 or variable mark densities, which are essential for effective testing at speeds of multi-Gb/s.

In this paper we present a relatively low cost IC, developed in an advanced SiGe BiCMOS 0.25um process with an fTof 80 GHz, which could act as a simple BERT. This IC is capable of generating PRB sequences of lengths 2 31 -1, 2 23 -1, 2 15 -1, 2 10 -1 & 2 7-1 with mark densities of 1/2, 1/4 & 1/8 for each of the patterns.

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Peter Habicht, Lead Consultant
Peter specializes in welding and metallurgical engineer with 40 years industry experience in commercial nuclear power plant construction.


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